The present invention relates generally to the testing of integrated circuit devices, and more specifically to the testing of synchronous integrated circuit devices having a stress test mode or other test mode.
Stress test modes are commonly used in modern synchronous integrated circuit devices to subject the integrated circuit device to various types of tests which “stress” the device. It is important to stress various element and signals of the device for maximum fault coverage. For instance, the external clock signal supplied to the integrated circuit device is an important signal to test because it controls many of the gates contained within the device. Thus, for maximum fault coverage of the device, it is important to stress the external clock signal both at a low logic state and a high logic state. Difficulties are encountered in trying to establish the logic states of the device during a stress test mode. These difficulties are encountered in a memory cell stress test mode of the device, in which all rows and columns are enabled and bitlines true or bitlines complement of the memory cell are pulled to power supply voltage VSS, or in a periphery stress test mode in which all rows and columns of the device are disabled. The difficulty lies in the fact that master/slave latches on the inputs of the integrated circuit device do not allow data to flow all the way through the device since only one master latch or one slave latch will conduct at a time.
Another prior art problem encountered with synchronized integrated circuit test modes is that entering a test mode after the integrated circuit device has been powered-up can result in device latch-up. Once the device powers-up, it has initialized to a certain voltage, such as 3 volts or 5 volts. Transition to a test mode from this voltage condition causes huge current spikes which can result in device latch-up as all the rows, columns, bitlines, etc. of the device simultaneously switch from a normal operation mode to a test mode. It would thus be desirable to enter a test mode upon power-up of the device in order to avoid possible device latch-up.
There is thus an unmet need in the art to be able to initialize the entire data path of an integrated circuit device in a test mode during device power-up and to be able to adequately test the external clock signal of the device or a derivative clock signal thereof in both a high logic state and a low logic state.